//Program simulates an and gate

module andchip(A,B,C);

input A,B;

output C;

assign C=(A&B);

endmodule

module stimckt;

reg[1:0]D;

wire C;

andchip and1(D[1],D[0],C);

initial

begin

D=2'b00;

repeat(4)

#10 D=D+1'b1;

end

initial

$monitor("Time=%0d,AB=%b C=%b",$time,D,C);

endmodule