//Program simulates a 4 bit ripple binary counter chip

module binary_Counter(Q,R1,R1,CLK);

output Q;

input R1,CLK;

reg [3:0]Q;

always @ (posedge R1 or posedge CLK)

if ((R1))

Q=4'b0000;

else if (CLK)

Q=Q+4'b0001;

endmodule

//Provides stimulation to 4 bit binary ripple counter chip

module stimckt;

reg R1,CLK;

wire [3:0]Q;

binary_Counter bn1(Q,R1,R1,CLK);

initial

begin

R1=1'b1;

#10 R1=~R1;

end

initial

begin

#5 CLK=1;

repeat(40)

#5 CLK=~CLK;

end

initial

$monitor("time=%0d, R1=%b, clock=%b, Q=%b",$time,R1,CLK,Q[3],Q[2],Q[1],Q[0]);

endmodule