//Program simulates a D FLIP FLOP chip

module D_FLIPFLOP(CLR,PRST,CLK,D,Q,QNOT);

output Q,QNOT;

input CLR,PRST,CLK,D;

reg Q,QNOT;

always @ (CLR or PRST or posedge CLK)

if ((~CLR) & (~PRST))

begin

Q=1'b1;

QNOT=1'b1;

end

else if (~CLR)

begin

Q=1'b0;

QNOT=1'b1;

end

else if (~PRST)

begin

Q=1'b1;

QNOT=1'b0;

end

else

begin

Q=D ;

QNOT=~D;

end

endmodule

//Provides stimulation to latch chip

module stimckt;

reg [1:0]A;

reg CLK,D;

wire Q,QNOT;

D_FLIPFLOP DFF(A[1],A[0],CLK,D,Q,QNOT);

initial

begin

A=2'b00;

repeat(3)

#10 A=A+1'b1;

//#40 $finish;

end

initial

begin

#5 CLK=1;

repeat(9)

#5 CLK=~CLK;

end

initial

begin

#5 D=1'b1;

repeat(5)

#10 D=~D;

end

initial

$monitor("time=%0d, clear=%b, preset=%b, D=%b, Q=%b, QNOT=%b",$time,A[1],A[0],D,Q,QNOT);

endmodule