//Program simulates a nand gate

module nandchip(C,A,B);

input A,B;

output C;

assign C=~(A&B);

endmodule

//Program models an or by nand gates

module or_by_nandchip(C,A,B);

input A,B;

output C;

wire w1,w2;

nandchip n1(w1,A,A);

nandchip n2(w2,B,B);

nandchip n3(C,w1,w2);

endmodule

//Program stimulates an or by nand gates

module stimckt;

reg[1:0]D;

wire C;

or_by_nandchip nandor1(C,D[1],D[0]);

initial

begin

D=2'b00;

repeat(4)

#10 D=D+1'b1;

end

initial

$monitor("Time=%0d,AB=%b C=%b",$time,D,C);

endmodule